Digital communication channels are used in a variety of applications. One area of advancement is in increasing the amount of data which can be encoded into a channel of a given bandwidth. When applied to tape or disk drives, increasing the channel data rate while keeping the bandwidth constant produces a corresponding increase in the linear density of recorded data. However, a problem arises as the channel data rate increases while bandwidth is held constant: individual symbols spread so much that they interfere with sample values of adjacent intervals.
One way to deal with intersymbol interference is to purposely introduce a prescribed amount of intersymbol interference which is accounted for in the detection circuitry. One such technique is the well-known Partial Response (PR) signaling. In PR signaling, channel filters limit the spectrum so that the main part of each pulse extends across more than one signal interval and contributes to more than one sample time. A particular arrangement of PR signaling, in which the pulse is exactly three clock periods wide at its base, is known as PR Class 4 (PR4).
Problems arise with PR4 detection channels at high linear densities. Such channels require a great deal of equalizer boost. This requires the use of an expensive and complex multi-stage equalizer having considerable power consumption. For example, in some integrated decoding channels, the equalizer may use as much as half of the chip power dissipation. In addition, such equalization amplifies the noise in the channel, which may result in unreliable clocking.